A sub optimal situation is when the number of states is reduced, but the number of flip flops is not. For example if a finite state machine drops from 7 states to 4 states and compact state assignment are used, the design drops from three flip flops to two flip flop. If one is able to reduce the total number of states, one may be able to save on the number of flip flops required for a design. Races can be avoided by directing the circuit through a unique sequence of intermediate unstable states when a circuit does that, it is said to have a cycle. The transition tables below illustrate critical races: If the final stable state that the circuit reaches does not depend on the order in which the state variable change, the races are illustrated in the transition tables below: The resulting logic diagram is shown below:Ī race condition exists in an asynchronous circuit when two or more binary state variables change value in response to a change in an input variable, when unequal delays are encountered a race condition may cause the state variable to change in an unpredictable manner. This assignment converts the flow table into a transition table. In order to obtain the circuit described by a flow table, it is necessary to assign to each state distinct value. In a flow states are named by letter symbols. The table provides the same information as the transition table.
The state table of the circuit shown below: The circuits has four stable total states –y 1y 2x= 000, 011, 110, and 100 and four unstable total states 001, 010, 111, and 100.
Those where Y=y are circled to indicate a stable condition. The transition table shows the values of Y=Y 1Y 2 inside each square. The next step is to plot the Y 1 and Y 2 functions in a map:Ĭombining the binary values in corresponding squares the following transition table is obtained. The analysis of the circuit starts by considering the excitation variables (y 1 and y 2).Īs outputs and the secondary variables (y 1 and y 2) as inputs. TRANSITION TABLEĪn example of an asynchronous sequential circuit is shown below: Boolean expressions are written and then transferred into tabular form. The analysis of asynchronous sequential circuits proceeds in much the same way as that of clocked synchronous sequential circuits. The next state variables (y 1 and y 2) are called excitation variables.įundamental mode operation assumes that the input signals change one at a time and only when the circuit is in a condition. The present state variables (y 1 and y 2) are called secondary variables. There are n input variables, m output variables, and k internal states. The communication of two units, with each unit having its own independent clock, must be done with asynchronous circuits.
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